The development of large monolithic dynamic random access memories has run into many problems. For example, one major problem involves shrinking the DRAM cell size without degrading retention time of the stored charge in order to pack more cells on a chip.
Large DRAMs are silicon based. Each DRAM cell typically includes a single MOS field effect transistor, a charge transfer device, with one of its source/drain diffusions connected to a storage capacitor. The other of the source/drain diffusions of the MOSFET typically is connected to a bit line. The gate typically is connected to a word line.
The DRAM cell operates by storing a charge on the capacitor for a logic 1 and not storing any charge for a logic 0. To maintain stable circuit operation the capacitance must be large enough and the charge transfer device must retain the stored charge, to yield a sufficient signal to noise ratio.
As DRAM cells are scaled to meet a chip size requirement for 1 G bit and generations beyond, the channel length of a transfer device on the substrate surface can no longer be scaled without degrading sub-threshold leakage requirements or retention time requirements.